In a computer architecture, a bus provides an interconnection of the various components and devices coupled to the system (e.g., CPU, memory, peripherals, and other external computing devices) and generally carries some combination of power, data, and commands among the components. There are varieties of bus types and all buses fall into one of two categories: serial or parallel. Some examples of parallel buses include ISA, Microchannel, AGP, and so on. Some examples of serial buses include PCI express, SPI bus, and so on.
In most common personal computers, a core logic chipset routes input and output (I/O) traffic among the various components and devices coupled to the system. The core logic chipset is typically split into two parts: the North Bridge and the South Bridge. The CPU, and the main memory are connected together by the North Bridge and communicate via a front side bus. The North Bridge may also connect to other devices attached to various bus interfaces including, PCI, PCI Express, AGP, and so on. The North Bridge is also connected to the South Bridge, the secondary bridge that routes traffic to and from an assortment of I/O devices on the system, e.g., hard disk drives, Ethernet ports, and so on. The traffic from these devices goes through the South Bridge to the North Bridge and then on to the CPU and/or memory.
Many systems use a PCI bus to connect devices to the system. PCI uses a shared bus topology in which all of the different PCI devices communicate with the CPU over the same bus physical connections. Increasingly, systems are switching to PCI Express which uses point-to-point connections between devices to provide greater bandwidth and device isolation. As with PCI, PCI Express devices are able to initiate memory reads and writes (DMA).
Systems based on x86 processors currently program DMA devices using physical memory addresses. This has limitations in making the system secure. A preferable way to handle this is to have a means of translating addresses from DMA devices so that the DMA device can be constrained to work in a more restricted address space. Intel and others are in the process of adding DMA remapping capability to the “central complex” (e.g. the North Bridge, the CPU and memory). Virtual addresses from DMA devices will be translated by logic in the central complex before being presented to the memory system. So that it is not necessary to do an expensive (in time) table lookup every time a virtual DMA address is presented, it is expected that the central complex will be able to cache some number of the translations so that they can be found quickly without reference to memory tables. The address translation cache is often called a Translation Look-aside Buffer or TLB. The TLB would be included in the chipset along with the engine that performs the translation. The problem with this approach is that it is difficult to design the TLB in the central complex to be the right size for all applications. In some systems, the TLB can be fairly small as the number of DMA devices is small and their rate of DMA is low. In other systems, the number of DMA devices is large and their access rate is very high. Each of these different system types requires a different size of TLB.